Performance of computer processors has increased exponentially for much of the past half century. Continued improvement in processing performance requires the constant development of new technologies and methods. One known performance improvement technique involves the use of a processor cache. The cache offers greatly improved data access fines over the main memory, but is limited in its storage capacity. Due to the performance enhancements they offer, caches have seen near uniform adoption in the field.
Another technology used to improve processor performance is the use of multiple processors in parallel. In these scenarios, when a system uses multiple processors, the various processing cores may share access to a single cache. This beneficially allows each processor to read data that was cached by another processor. However, if each the plurality of processors accesses different portions of a file in parallel, the memory accessed by each processor is likely to be spatially distant (that is, likely to be located at rows and columns of the memory far away from one another). For that reason, in such scenarios there is a substantial likelihood that the processors may request data that maps to the same cache line, creating a conflict. Cache conflicts are costly, causing the processor to read from the main memory instead, leading to substantially reduced performance. Accordingly, there is a need to improve cache performance for use with multiple processors in parallel when the parallel processors are likely to access spatially distant portions of a file in memory.